Device for Data Storage and Processing, and Method Thereof

A device for data storage and processing includes: at least two input racetrack elements having a plurality of first magnetization regions; at least one output racetrack element having a plurality of second magnetization regions, wherein a magnetization vector is adapted to switch from a first direction to the opposite one, or vice versa, by way of a magnetic field of reduced intensity compared with a magnetic field required to produce a similar switching of a magnetization vector of the first magnetization region, wherein the input racetrack elements and output racetrack element are configured in such a way as to constitute at least one elementary logic gate, wherein at least two of the first magnetization regions are magnetically coupled to at least one of the second magnetization regions

RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures

Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as the "memory wall" and severely limits the performance of a microprocessor. One of the most promising solutions is the "logic-in-memory" approach. It consists of merging memory and logic units, enabling data to be processed directly inside the memory itself. Here we propose an RISC-V framework that supports logic-in-memory operations. We substitute data memory with a circuit capable of storing data and of performing in-memory computation. The framework is based on a standard memory interface, so different logic-in-memory architectures can be inserted inside the microprocessor, based both on CMOS and emerging technologies. The main advantage of this framework is the possibility of comparing the performance of different logic-in-memory solutions on code execution. We demonstrate the effectiveness of the framework using a CMOS volatile memory and a memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in algorithm execution speed and a reduction in energy consumption

ERIC: An Efficient and Practical Software Obfuscation Framework

Modern cloud computing systems distribute software executables over a network to keep the software sources, which are typically compiled in a security-critical cluster, secret. We develop ERIC, a new, efficient, and general software obfuscation framework. ERIC protects software against (i) static analysis, by making only an encrypted version of software executables available to the human eye, no matter how the software is distributed, and (ii) dynamic analysis, by guaranteeing that an encrypted executable can only be correctly decrypted and executed by a single authenticated device. ERIC comprises key hardware and software components to provide efficient software obfuscation support: (i) a hardware decryption engine (HDE) enables efficient decryption of encrypted hardware in the target device, (ii) the compiler can seamlessly encrypt software executables given only a unique device identifier. Both the hardware and software components are ISA-independent, making ERIC general. The key idea of ERIC is to use physical unclonable functions (PUFs), unique device identifiers, as secret keys in encrypting software executables. Malicious parties that cannot access the PUF in the target device cannot perform static or dynamic analyses on the encrypted binary. We develop ERIC's prototype on an FPGA to evaluate it end-to-end. Our prototype extends RISC-V Rocket Chip with the hardware decryption engine (HDE) to minimize the overheads of software decryption. We augment the custom LLVM-based compiler to enable partial/full encryption of RISC-V executables. The HDE incurs minor FPGA resource overheads, it requires 2.63% more LUTs and 3.83% more flip-flops compared to the Rocket Chip baseline. LLVM-based software encryption increases compile time by 15.22% and the executable size by 1.59%. ERIC is publicly available and can be downloaded from https://github.com/kasirgalabs/ERICComment: DSN 2022 - The 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Network

MEMRISTOR BASED SENSOR

A sensor comprises a plurality of sensor elements arranged in an array . Each sensor element is memristive and has an electrical resistance characteristic related to exposure to a species to be sensed . The sensor elements are arranged to be connectable such that at least one sensor element is connected in parallel with at least one other sensor element . By using appropriate connections , the array of sensor elements can be read

Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures

Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Toward this, emerging memories featuring computational capacity are foreseen as a promising solution that performs data process inside the memory itself, so-called computation-in-memory, while eliminating the need for costly data movement. Recent research shows that utilizing the custom extension of RISC-V instruction set architecture to support computation-in-memory operations is effective. To evaluate the applicability of such methods further, this work enhances the standard GNU binary utilities to generate RISC-V executables with Logic-in-Memory (LiM) operations and develop a new gem5 simulation environment, which simulates the entire system (CPU, peripherals, etc.) in a cycle-accurate manner together with a user-defined LiM module integrated into the system. This work provides a modular testbed for the research community to evaluate potential LiM solutions and co-designs between hardware and software

Thoracic Endovascular Aortic Repair for Type B Acute Aortic Dissection Complicated by Descending Thoracic Aneurysm

OBJECTIVES: To analyse the results and review the literature about thoracic aortic endovascular repair (TEVAR) for type B acute aortic dissection (TBAAD) complicated by descending thoracic aortic aneurysm (DTA) in the hyperacute or acute phases. METHODS: This was a multicentre, observational descriptive study. Inclusion criteria were TBAAD with a DTA of 6550 mm, TBAAD on an already known aneurysmal descending thoracic aorta, and TBAAD presenting with an enlarged aorta with a total diameter <50 mm, but with >50% diameter increase compared with a previous computed tomography angiography (CTA) showing a non-dissected aorta with normal sizing. Primary endpoints were early and long-term survival, freedom from TEVAR and aortic related mortality (ARM), and freedom from re-intervention. RESULTS: Twenty-two patients were included in the analysis. The mean aortic diameter was 66 \ub1 26 mm (range 42-130; IQR 51-64). The in hospital TEVAR related mortality was 14% (n = 3). The mean radiological follow-up was 56 \ub1 45 months (range 6-149; IQR 12-82), and the follow-up index 0.97 \ub1 0.1. All surviving patients were available for follow-up. During follow-up the cumulative mortality was 26% (n = 5) and TEVAR related mortality was 5% (n = 1). Overall the estimate of survival was 82% (95%CI: 61.5-93) at 1 year, and 64% at 5 years. Ongoing primary clinical success was 79% (re-intervention n = 4). Freedom from aortic related mortality was 86% (95%CI: 66-95) at 1 and 5 year, while freedom from re-intervention was 95% (95%CI: 75.5-95) at 1 year, and 77% (95%CI: 50-92) at 5 years. CONCLUSIONS: In our experience, DTA is a frequent complication from the very beginning of the clinical onset of TBAAD. In this high-risk cohort, TEVAR showed satisfactory results, better than those predicted by the risk score for open repair, with favourable stability of the aortic diameter and no aortic related adverse events during follow-up